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IBM v5.2 answers
IP Processor Core Platform option in response to SoC structure: a case examine | 000-079 Latest Questions and test Questions
via Aoudni Yassine, GMS/LESTER LaboratoriesSfax/Lorient, Tunisia/Francesummary:
This work aims to compare a few IP core processor based mostly systems in line with right here key parameters: FPGA structure, coprocessor and accelerator integration, RTOS and HW-SW refinement equipment. These key parameters are required to select a versatile and high efficiency IP processor core (and the associated equipment) so as to enforce an efficient monoprocessor PACM (Processor – Accelerator – Coprocessor – memory) architecture model. A case analyze for the PACM structure mannequin has been centered with the intention to validate our key parameters. 4 IP processor cores have been candidate to put into effect the PACM structure model. finally, the selected ones corresponds to the Nios tender processor core within its development equipment (Quartus, SOPC Builder and STRATIX equipment) and a shading algorithm for 3D picture remedy changed into carried out to show the IP processor core platform adequacy with our PACM structure model.
1. Introduction
The designs of SoC in many utility domains are sometimes subject to stringent requirements in terms of processing efficiency and suppleness [1]. To permit flexible cost-effective designs in a brief design cycle, rising designs are based on hardware/utility SoC systems that integrate numerous processor cores as programmable elements along with dedicated hardware (HW) accelerators inside a single reasonably-priced chip. Programmability is introduced in these single-chip architectures (as a consequence providing the desired flexibility in the design), whereas keeping lots of the benefits of custom-made VLSI options (such as the capabilities to optimize the processing efficiency and power dissipation) [2].
Hardware/software co-design formula exists nowadays for designing the distinct hardware and software supplies of a SoC architecture [3]. As time to market pressures and product complexities climb, the deserve to reuse advanced building (often known as intellectual Property (IP) or virtual part (VC)) additionally raises. These components signify processor architectures (RISC, SPARC…) and functions for selected area like sign processing (DCT, FFT), telecommunication and multimedia (VLC, rapid codes) etc. in this enviornment, SoC implementation management requires a strong codesign atmosphere as a way to master the complexity and the different refinement steps of the device from a high level specification.
reckoning on the software, distinctive utility-particular architectures using different execution models and mixtures of application and hardware components can be required (e.g. driven by using programmability, efficiency, and power computing necessities). Even the choice of the programmable processor to make use of is closely dependent on the application. briefly, the question to reply is: can the equal IP processor core prototyping platforms [4] handle all structure fashions or is there a alternate-off between these structures and structure fashions? in this paper we suggest a solution and exhibit it the usage of our case look at.
determine 1: SoC architecture mannequin in accordance with a processor core
A classical mono-processor SoC architecture model is depicted in figure 1. this is the mannequin we now have selected to implement the PACM (Processor – Accelerator – Coprocessor – reminiscence) architecture mannequin as might be explained in here.
This paper gifts a case look at evaluation of a few IP processor cores prototyping platforms to choose the proper ones for the goal architecture (see figure 1). at the beginning, we existing the comparative study between IP processor cores based mostly systems and the important thing parameters of alternative extracted from the PACM architecture mannequin. A 3D shading algorithm instance has been implemented to reveal the IP processor core platform adequacy with our PACM structure model. ultimately, we conclusion with conclusion.
2. IP processor core platform for the PACM structure mannequin
during this area, for the structure introduced in figure 2 and according to the model presented in determine 1, we reveal that a number of IP processor cores platforms, identical in first view, don't present the equal adequacy diploma with the focused model of execution. The figure 3 presents the PACM model. definitely our architecture is developed around a processor core (for example Nios, ARM, LEON…) which presents configuration alternatives for including coprocessors reached during the main processor registers (as an instance floating point unit, HW divider, HW mathematic capabilities ...).
figure 2: PACM architecture
The processor communicates with committed HW accelerators via a common on chip HW/SW bus (e.g. Amba, Avalon, IBM CoreConnect…) the use of manage common sense and certain reminiscence blocks.
Coprocessors and HW accelerators usage depends upon the application complexity and on the computing constraint necessities. so as to give extra flexibility and adaptableness to the SoC, we now have chosen the reconfigurable know-how to put in force our SoC.
If we analyze the important thing parameters of the PACM architecture model, the adequate IP processor core platform should integrate the following aspects:
All these key parameters correspond to the standards to opt for an appropriate IP processor core platform. We made a qualitative look at for different representative IP processor core systems, and evaluate their adequacy with the PACM architecture mannequin.
desk 1 : IP processor core systems comparaison
We performed an experimental study in accordance with the leading aspects of IP processor core systems. The consequences are introduced in table 1. We be aware that each one presented IP processor core structures supply a robust and efficient HW and SW refinement tools like ISE Xilinx device and Quartus, on chip HW/SW bus as AMBA (LEON and ARM Excalibur kits) and IBM CoreConnect (PowerPC and Microblaze kits) and additionally a port for many RTOS like RTEMS port on LEON and ARM, WindRiver port on PowerPC and Microblaze, etc. however, best Nios, ARM and LEON IP cores can assist coprocessor characteristic. in addition, coprocessor integration in Nios and ARM IP cores is more fast and flexible the use of the virtualization and customized guideline generation given with the aid of SOPC Builder user-chum device. also, Nios SoC can be applied in significant STRATIX household [9] which consists of DSP blocks and different sizes of RAM blocks, in contrast to ARM development equipment which is restricted to APEX gadget and its core is a hard IP and never a tender one just like the Nios core. therefore, we note that the SoC platform in line with Nios IP processor core [10] supplied with Quartus and SOPC Builder environments by Altera [11] is probably the most appropriate to design a reconfigurable SoC in accordance with IP processor core the use of the PACM architecture model. certainly, SOPC Builder device gives the clothier a digital photo of the Nios processor smooth core and the accelerators may also be linked to the Nios processor core in the course of the Avalon on chip bus. custom guidelines are additionally offered with this platform with a purpose to facilitate the coprocessors integration within the Nios ALU. namely, our alternative is according to this ultimate function to be able to put into effect a reconfigurable ASIP core.
As a conclusion of this evaluation we can see that the purchasable IP processor cores structures can't tackle all the SoC architecture fashions and that a examine ought to be executed to be able to opt for the relevant IP processor core platform for the applicable architecture model. In our case the Nios processor core package is relevant to the PACM structure model.
within the next area, to illustrate the efficiency of using the Nios processor core equipment to enforce the PACM architecture model we latest a case examine on shading algorithms for 3D picture medication. Our platform consists of Quartus and SOPC Builder environments, Nios delicate core processor, an EP1S40 STRATIX equipment and the MicroC/OS-II RTOS [12]. be aware that the RTOS implementation will be achieved in future work.
three. Experimentation case examine
during this case look at, we've applied two 3D shading algorithms used in picture synthesis: LAMBERT and GOURAUD [13]. These algorithms consist to cut an object in a couple of polygons after which to assess the intensity of the easy in each polygon of the thing. a number of mathematic expressions and vectors analysis must be achieved to be able to get a light-weight intensity price for one polygon. The simple operations of those computing operations are the addition, subtraction, multiplication and square root. indeed, for every polygon we should calculate the enviornment typical vector, light course vector and the perspective between these two vectors. The change between both algorithms is that GOURAUD takes into consideration the continuity between neighbours polygons not like LAMBERT (see determine 3a and 3b).
LAMBERT and GOURAUD algorithms can also be applied in the Nios as a SW program. however to be able to speed up the execution an answer consists to use HW accelerators. a different solution can also be achieved via extracting coprocessors from the SW execution in order to speedup some crucial ingredients of
figure 3a: shading with LAMBERT algorithm
figure 3b: shading with GOURAUD algorithm
the code. In accepted these critical elements correspond to nested loop body operations that are achieved a large variety of time. These two sorts of implementation are presented in right here paragraphs correct after the full SW algorithms implementation.
at first, we carried out these two algorithms as two accelerators linked to the Avalon on chip bus. certainly within the Quartus ambiance, we are able to design a HW accelerator the usage of a Block Design File (BDF) as offered in figure 4, then we can generate the selected VHDL or Verilog code and at last we can run the compilation to simulate and to get the bit circulate file. The BDF feature in Quartus ambiance helps the dressmaker to get a right HDL code in much less time with optimized components supplied in the supplier library. we've used the PIO interface feature in SOPC Builder to hyperlink the HW accelerators with the Avalon bus. This tool is in a position to generate immediately the interface between the HW and the SW add-ons it's helpful to cut back the HW/SW SoC time design.
figure four: LAMBERT and GOURAUD Block Design data
Secondly, we integrated mathematic coprocessors as customized guidance inside the Nios smooth core. in this case, the digital design entry of the Nios in SOPC Builder is terribly beneficial and efficient to configure the processor core, exceptionally for including both 16 or 32 bits coprocessors via two leading ALU registers. the important thing point in this feature is the era of specific coprocessor custom guide prevalent through the Nios C compiler.
table 2: consequences obtained for the LAMBERT and GOURAUD algorithms
desk 2 gives the outcomes got for the LAMBERT and GOURAUD algorithms the use of the accelerators and the coprocessors. The results are given in term of required good judgment elements and in term of execution time speedup compared to a full software implementation the usage of the Nios. we are able to note that the speedup bought using GOURAUD accelerator is more important than the coprocessor one, but it wants greater enviornment (i.e. FPGA resources). on the other hand coprocessors LAMBERT implementation is extra advantage than accelerator ones when it comes to logic mobile and speedup. thus, the alternative between accelerators or coprocessors implementation depends on the SoC execution time and FPGA components constraints. notice that the usage of this SoC platform a number of workdays are only vital for a pretty good implementation of these two complicated algorithms which prove the efficiency of the key parameters to opt for a SoC platform for the PACM architecture model.
four. Conclusion
in this paper and in keeping with the PACM architecture mannequin, we have proven that the available IP processor cores platforms cannot handle the entire SoC architecture fashions and an analysis ought to be completed to choose the correct IP processor core platform for the acceptable structure mannequin. the key parameters that we have considered to opt for the right IP processor core platform are right here ones: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement equipment in line with these parameters a platform in accordance with the Nios STRATIX development equipment became chosen to put in force the PACM structure model. To validate our option two 3D shading algorithms were implemented on the Nios platform the usage of the Quartus and SOPC Builder. consequences have Checked the benefits using such platform for the PACM structure model. In future work, we suggest to implement the RTOS subroutine and to look at the SoC power performance for the PACM structure with video compression algorithms.
References
[1] Julio C, B.Mattos, Luigi Carro, effective structure for FPGA-based mostly microcontrollers, ISCAS paper number 2825, 2002.
[2] Amit Singh, Malgorazta Marker-Sadowska, effective circuit clustering for area and vigour discount in FPGAs, SIGDA 2002.
[3] bill Lin, Karl Van Rompaey, Stenven Vercauteren, Designing single chip systems, ASIC 1996.
[4] M. Bolado1, H. Posadas1and All, Platform in accordance with Open-source Cores for Industrial functions, Design Automation and examine in Europe February sixteen-20, Paris DATE’2004.
[5] F. Campi, A. Cappelli,A. La Rosa, L. Lavagno,R. Canegallo, A Reconfigurable Processor structure and software construction environment for Embedded techniques, Reconfigurable structure Workshop, first-rate France uncooked’2003.
[6] Vesa Lahtinen, Kimmo Kuusilinna, Tero Kangas, Timo Hamalainen, Interconnection scheme for continuous-media techniques-on-chip, pages 123-138 Microprocessors and Microsystems 26, 2002.
[7] V. Nollet, P. Coene, D. Verkest, S. Vernalde, R. Lauwereins, Designing an working gadget for a Heterogeneous Reconfigurable SoC, Reconfigurable structure Workshop, nice France uncooked’2003.
[8] Y .Aoudni, I. Maalej and al., evaluation of difficult ware/application system on Chip: Case examine, IEEE4. Conclusion